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Xilinx XCV812E-7BG560I FPGA &CPLD Boards
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XCV812E-7BG560I Tech Specifications
Xilinx XCV812E-7BG560I technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
| Surface Mount | YES | |
| Number of Terminals | 560Terminals | |
| Manufacturer Part Number | XCV812E-7BG560I | |
| Rohs Code | No | |
| Part Life Cycle Code | Obsolete | |
| Ihs Manufacturer | XILINX INC | |
| Part Package Code | BGA | |
| Package Description | PLASTIC, BGA-560 | |
| Risk Rank | 5.85 | |
| Clock Frequency-Max | 400 MHz | |
| Moisture Sensitivity Levels | 3 | |
| Operating Temperature-Max | 85 °C | |
| Operating Temperature-Min | -40 °C | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | LBGA | |
| Package Equivalence Code | BGA560,33X33,50 | |
| Package Shape | SQUARE | |
| Package Style | GRID ARRAY, LOW PROFILE | |
| Supply Voltage-Max | 1.89 V | |
| Supply Voltage-Nom | 1.8 V | |
| Reflow Temperature-Max (s) | 30 | |
| Supply Voltage-Min | 1.71 V | |
| JESD-609 Code | e0 | |
| Pbfree Code | No | |
| ECCN Code | 3A991.D | |
| Terminal Finish | Tin/Lead (Sn63Pb37) | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | BOTTOM | |
| Terminal Form | BALL | |
| Peak Reflow Temperature (Cel) | 225 | |
| Terminal Pitch | 1.27 mm | |
| Reach Compliance Code | not_compliant | |
| Pin Count | 560 | |
| JESD-30 Code | S-PBGA-B560 | |
| Number of Outputs | 404Outputs | |
| Qualification Status | Not Qualified | |
| Power Supplies | 1.2/3.6,1.8 V | |
| Temperature Grade | INDUSTRIAL | |
| Number of Inputs | 404Inputs | |
| Organization | 4704 CLBS, 254016 GATES | |
| Seated Height-Max | 1.7 mm | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Combinatorial Delay of a CLB-Max | 0.42 ns | |
| Number of CLBs | 4704CLBs | |
| Number of Logic Cells | 21168Logic Cells | |
| Number of Equivalent Gates | 254016Equivalent Gates | |
| Length | 42.5 mm | |
| Width | 42.5 mm |
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