STMicroelectronics PSD312RB-70J Embedded FPGAs
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PSD312RB-70J Tech Specifications
STMicroelectronics PSD312RB-70J technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
| Package / Case | PLCC | |
| Surface Mount | YES | |
| Number of I/Os | 19I/Os | |
| Operating Temperature (Max.) | 70°C | |
| JESD-609 Code | e0 | |
| Number of Terminations | 44Terminations | |
| ECCN Code | EAR99 | |
| Terminal Finish | Tin/Lead (Sn/Pb) | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | QUAD | |
| Terminal Form | J BEND | |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
| Supply Voltage | 5V | |
| Terminal Pitch | 1.27mm | |
| Reach Compliance Code | not_compliant | |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
| Pin Count | 44 | |
| JESD-30 Code | S-PQCC-J44 | |
| Qualification Status | Not Qualified | |
| Supply Voltage-Max (Vsup) | 5.5V | |
| Power Supplies | 5V | |
| Temperature Grade | COMMERCIAL | |
| Supply Voltage-Min (Vsup) | 4.5V | |
| Number of Ports | 3Ports | |
| uPs/uCs/Peripheral ICs Type | PARALLEL IO PORT, GENERAL PURPOSE | |
| Standby Current-Max | 0.00002A | |
| Access Time (Max) | 7e-8 ns | |
| UV Erasable | N | |
| ROM Size (bits) | 524288Bits | |
| Length | 16.56mm | |
| Height Seated (Max) | 4.57mm | |
| Width | 16.56mm | |
| RoHS Status | Non-RoHS Compliant |
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