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PHN210T,118 Tech Specifications

Nexperia  PHN210T,118 technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.

Factory Lead Time 16 Weeks
Mounting Type Surface Mount
Package / Case 8-SOIC (0.154, 3.90mm Width)
Surface Mount YES
Number of Pins 8Pins
Transistor Element Material SILICON
Number of Elements 2 Elements
Turn Off Delay Time 21 ns
Operating Temperature -65°C~150°C TJ
Packaging Tape & Reel (TR)
Series TrenchMOS™
Published 2010
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8Terminations
Termination SMD/SMT
ECCN Code EAR99
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Additional Feature LOGIC LEVEL COMPATIBLE
Max Power Dissipation 2W
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 8
Element Configuration Dual
Operating Mode ENHANCEMENT MODE
Power Dissipation 2W
Turn On Delay Time 6 ns
FET Type 2 N-Channel (Dual)
Transistor Application SWITCHING
Rds On (Max) @ Id, Vgs 100m Ω @ 2.2A, 10V
Vgs(th) (Max) @ Id 2.8V @ 1mA
Input Capacitance (Ciss) (Max) @ Vds 250pF @ 20V
Gate Charge (Qg) (Max) @ Vgs 6nC @ 10V
Rise Time 8ns
Fall Time (Typ) 15 ns
Continuous Drain Current (ID) 2.4A
Threshold Voltage 2V
JEDEC-95 Code MS-012AA
Gate to Source Voltage (Vgs) 20V
Max Dual Supply Voltage 30V
Drain Current-Max (Abs) (ID) 3.4A
Drain-source On Resistance-Max 0.1Ohm
Drain to Source Breakdown Voltage 30V
Pulsed Drain Current-Max (IDM) 14A
Dual Supply Voltage 30V
Avalanche Energy Rating (Eas) 13 mJ
FET Technology METAL-OXIDE SEMICONDUCTOR
FET Feature Logic Level Gate
Nominal Vgs 2 V
Height 1.45mm
Length 5mm
Width 4mm
REACH SVHC No SVHC
Radiation Hardening No
RoHS Status RoHS Compliant
Lead Free Lead Free
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PHN210T,118 Documents

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