Altera Corporation EP312PC-30 Programmable Logic Devices
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EP312PC-30 Tech Specifications
ALTERA EP312PC-30 technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
| Surface Mount | NO | |
| Number of Terminals | 24Terminals | |
| Operating Temperature-Max | 70 °C | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | DIP | |
| Package Equivalence Code | DIP24,.3 | |
| Package Shape | RECTANGULAR | |
| Package Style | IN-LINE | |
| Supply Voltage-Max | 5.25 V | |
| Supply Voltage-Min | 4.75 V | |
| Supply Voltage-Nom | 5 V | |
| Number of I/O Lines | 12I/O Lines | |
| Clock Frequency-Max | 50 MHz | |
| Package Description | DIP, DIP24,.3 | |
| Part Package Code | DIP | |
| Ihs Manufacturer | ALTERA CORP | |
| Part Life Cycle Code | Obsolete | |
| Rohs Code | No | |
| JESD-609 Code | e0 | |
| Pbfree Code | No | |
| Terminal Finish | TIN LEAD | |
| Additional Feature | 12 MACROCELLS | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | DUAL | |
| Terminal Form | THROUGH-HOLE | |
| Peak Reflow Temperature (Cel) | 220 | |
| Terminal Pitch | 2.54 mm | |
| Reach Compliance Code | unknown | |
| Pin Count | 24 | |
| JESD-30 Code | R-PDIP-T24 | |
| Number of Outputs | 12Outputs | |
| Qualification Status | Not Qualified | |
| Temperature Grade | COMMERCIAL | |
| Propagation Delay | 30 ns | |
| Architecture | PAL-TYPE | |
| Number of Inputs | 22Inputs | |
| Organization | 8 DEDICATED INPUTS, 12 I/O | |
| Seated Height-Max | 4.318 mm | |
| Programmable Logic Type | OT PLD | |
| Output Function | MACROCELL | |
| Number of Dedicated Inputs | 8Dedicated Inputs | |
| Number of Product Terms | 200Product Terms | |
| Width | 7.62 mm | |
| Length | 31.6865 mm |
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